PowerFactor Improvement of SinglePhase ACDC Systems Using Parallel Boost Converters

Power factor (PF) is a critical performance indicator for any system that draws alternating current from the grid. A low PF means the source current is out of phase with the voltage, resulting in higher RMS current, increased IR losses, and larger conductor sizing. In many industrial and residential applications, the input stage is a singlephase ACDC conversion that supplies a DC load (e.g., LED lighting, battery chargers, motor drives). Conventional diodebridge rectifiers, followed by a single boost converter, provide the required DC voltage but often at the expense of a poor PF, especially when the load is light.

Why Parallel Boost Converters?

Connecting multiple boost converters in parallel offers several advantages that can be harnessed to improve PF:

• Current Sharing: Each converter handles a fraction of the total current, reducing stress on individual switches and inductors.
• Modular Scalability: Adding or removing modules changes the rated power without redesigning the whole converter.
• Improved Dynamic Response: Parallel operation can be coordinated so that the combined inputside behavior mimics a controllable active frontend (AFE).
• Reduced Harmonics: By properly shaping the input current of each module, the overall current spectrum can be pushed toward the fundamental frequency.

Fundamentals of PowerFactor Correction (PFC)

In the context of a singlephase ACDC source, PF is defined as the cosine of the angle between the fundamental components of voltage v(t) and current i(t):

PF = cos() = \frac{P_{active}}{S_{apparent}}

For a perfect PF (unity), the input current must be sinusoidal and in phase with the supply voltage. Most rectifieronly topologies generate a highly nonsinusoidal current with a large harmonic content, causing PF values well below 0.8.

Operation of a Parallel Boost Converter System

Each boost converter in the parallel array consists of an input inductor L_i, a highfrequency switch (usually a MOSFET), a diode, and an output capacitor. The converters share a common DC output bus. The key to PF improvement lies in how the switches are controlled.

DualLoop Control Strategy

Two nested control loops are typically employed:

• Outer Voltage Loop: Regulates the DCbus voltage V_{bus} to the desired level (e.g., 400V). This loop provides the reference for each modules currentshaping controller.
• Inner CurrentShaping Loop: Generates a reference input current waveform that tracks a sinusoid proportional to the instantaneous line voltage.

The inner loop uses a peak current mode approach: the switch duty cycle is adjusted so that the peak inductor current follows a reference I_{ref}(t) = kV_{line}(t), where k is a gain set to achieve a desired PF. Because each module sees the same reference, the combined current supplied to the grid is also sinusoidal.

PhaseShifted Switching

To avoid undesirable current spikes when the modules start simultaneously, the switching signals are phaseshifted by 360/N, where N is the number of parallel converters. This technique distributes the ripple energy evenly across the AC cycle, reduces inputside current ripple, and improves overall harmonic performance.

Design Considerations

Selection of Inductor Value

The input inductor must store enough energy to sustain the boost operation while keeping the peak current within device limits. A common design formula is:

L_i = \frac{V_{in(min)}D_{max}}{If_s}

where D_{max} is the maximum duty cycle, I the allowable ripple, and f_s the switching frequency. Because the PF controller forces the inductor current to follow a sinusoid, a modest ripple (1015% of the average) is sufficient.

Switching Frequency Tradeoffs

Higher frequencies reduce the size of passive components but increase switching losses and generate higherorder harmonics. Typical values for PFC boost converters range from 100kHz to 500kHz. When several modules operate in parallel, the effective frequency perceived by the grid can be increased through interleaving, allowing a lower individual f_s while still achieving low ripple.

Current Sharing Control

Even though the PF controller determines the total input current, each module must share the load current on the DC side. A common method is to measure the modules output current and apply a small correction term to the duty cycle:

D_i = D_{PF} + K_{share}(I_{avg} - I_i)

where K_{share} is a lowgain constant, I_{avg} the average bus current, and I_i the individual modules current. This ensures that no single converter is overloaded.

Harmonic Reduction and Compliance

International standards such as IEC 6100032 place strict limits on the total harmonic distortion (THD) of input currents for equipment up to 16A. By shaping the input current to follow a sinusoid and by interleaving the switching actions, the parallelboost architecture can achieve THD values below 5%, comfortably meeting the standard.

Performance Illustration

Figure 1 Input voltage (blue) and current (red) of a parallelboost PFC system. The current is sinusoidal and in phase with the voltage, yielding PF 0.99.

A typical simulation of a threemodule parallel boost converter (each rated at 1kW) shows the following results under a lightload condition (200W total):

• Power factor: 0.985
• THD of line current: 3.8%
• Peak switch voltage: 620V (well within MOSFET rating)
• Input current ripple: 3% of the fundamental

Benefits Over Conventional SingleConverter PFC

• Higher Reliability: Failure of a single module reduces the overall power capacity but does not cause a complete shutdown.
• Thermal Management: Heat is spread across several devices, enabling lower temperature rises and longer component life.
• Flexibility: The same hardware can be repurposed for different power levels simply by adding or removing modules.
• Improved PF at Light Loads: Many singlestage PFC designs suffer PF degradation as load drops; interleaved parallel converters maintain a sinusoidal inputcurrent shape even at 5% of rated power.

Implementation Example

Below is a brief outline of the control algorithm that could be programmed in a DSP or microcontroller for a threemodule system.

// Constantsconst float kPF = 0.95;           // Desired PF gainconst float VlineRMS = 230.0;    // Line RMS voltage (V)const float Fs = 200e3;          // Switching frequency (Hz)const float N  = 3;              // Number of parallel modules// Measured quantities (sampled each PWM period)float VlineInst = readLineVoltage();   // Instantaneous line voltagefloat IbusAvg   = readBusCurrent();    // Average bus current// Calculate reference input current (peak mode)float IrefPeak = kPF * VlineInst / sqrt(2);// Phaseshifted duty for each modulefor (int i=0; i